Assura DRC Problems with IBM CMOS9RF

Hello all,
I'm learning layout in Cadence Virtuoso with IBM CMOS9RF. Now, when I create an NFET using pcell and run DRC with Assura, then I get error report informing that, the CA vias are too close to the device edges, as shown in Fig1, attached herewith. I could neither increase the areas of the drain and source regions nor could I stretch the rectangles of the device. So, I added RX layer around three edges (selected as white in Fig2) where the design rule was violated and passed the DRC then. My question is-
1. Is there any way of specifying or increasing the areas of the drain and source regions of the NFETs by the CDF of their pcell?
2. I increased the drain and source areas out of pcell- will it create any problem in LVS?
3. Is it possible to stretch the rectangles of the devices created using pcells?

Could anyone please share his experience with me in this regard?
Thank you,
Shahriar.

if the pcell is generating what is shown in Fig1, then there is a problem with the pcell and you should advise the foundry/vendor of this. if you want to stretch you must flatten the instance first.

Thanks for the reply.
Would you please mention what is the problem with the pcell, so that I can write precisely to the MOSIS. How the instance can be flattened?