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Spetre/Verilog simulator question

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malesky

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Dear all,

I am mew for analog cricuit design.I have IC5.1.41 & LDV5.1

Currently I use Spetreverilog simulator for a mixed-signal simulation.

After simulation ,there are 3 errors:
Error in cleaning up IPC in an attempt to quit.
Error in DC simulation for mixed-mode.
Error found by spectre during DC analysis during info "finalTimeOP" analysis skipped due to inability to compute operating point.

I have two questions:
(1)Maybe my DC oprating point is not right,but i don't know "IPC" in the first error meaning?
(2)Furthermore,when simulating my computer lost control ,sometimes icfb was killed. I want to know why?

thanks very much!
 

IPC I believe is compuGeek for "InterProcess Communication".
Probably the two simulators are not passing data cleanly,
one died or concluded when the other was not done (or failed
to start).

Verilog signals are sometimes "too ideal" for SPICE / Spectre
to deal with. I tend to put 1-ohm series resistors between
verilog / veriloga outputs and SPICE inputs to make sure that
too-ideal edges are mellowed out to where timestep can track.
I have no idea what a verilog block's "unknown" (X) output
might produce when presented to an analog simulator.
You might begin there, time zero, are all verilog ports
initialized to a valid high or low value?
 

thank you very much,dick_freebird!

I do just as you said to rewritten the verilog code and initialize the output value. Then simulation..... There comes no error and waveform appears. But the digitial output is constant all the time which is not right. I don't know where to put the 1-ohm resistor on schematic. I just put the resistor between a input analog source and a output digitial block, am i right?

Thanks again.
 

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