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Dynamic timing simulation

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raviram80

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Hi All,

I have the following questions

1. Why is gate level simulation called dynamic timing analysis.?

2. Why is static timing analysis called static ?

3. What are the differences between static timing analysis and dynamic?

Thanks,
 

dynamic timing simulation are vector based.
you will define some 1,0 at input ports and change them in testbench..

in static timing simulation vectors are not applied,you have to apply a clock only..
all timing paths in ur designs are checked for timing violations and worst case results are reported ...

e.g.
flop to flop timings path, setup/hold time violations will be tested for all inputs states going from one flop to another and failure will be reported...

key is
dynamic --> vector driven
static --> vectorless


dynamic runs with respect to time varying inputs so called dynamic
 

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