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MOS as switch --hvt or lvt better?

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eegchen

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hi ,

I am designing a MOS switch.
There are three types of threshold Voltage MOS, Low Vth, Normal Vth,and High Vth.
As i know, low vth can run high speed but large leakage. High is low speed, small leakage.

In the mos switch design, do you care about leakage ?

Best
Gang
 

It depends on the what impedance you required. In normal case, low Vt is preferred.
 

    E

    eegchen

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In a 50-ohm system you care very little about leakage. In a
sampled data analog system with a slow clock, you care a lot.
Work the requirements to define allowable leakage to not-fail
the relevant specs, and your choice should become clear.

You should see no more than an octave of speed difference
(presuming that commutation bandwidth matters at all;
through-bandwidth is an entirely different matter especially
in RF switching applications / designs) and there you would be
playing insertion loss and isolation against each other and the
best FET conduction density probably wins, with gate driver
attributes taking up the slack.
 

    E

    eegchen

    Points: 2
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i think you better tell much more information about your design
but if u you say the words only "switch", i guess better have a low Ron one
 

    E

    eegchen

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yeah, just as a normal switch used in switch cap circuit like Sample/Hold.

Added after 5 seconds:

yeah, just as a normal switch used in switch cap circuit like Sample/Hold.

Added after 2 minutes:

Thanks.
How can i know the requirements to define allowable leakage to not-fail the relevant specs
 

This is part of your job as a designer, to turn pin electricals
into block, component level requirements for your design.

In the case of the switch, as part of a sample/hold, you
probably have several concerns.

Input settling time - on resistance and the self- and explicit
hold capacitance give your time constant (presuming
no buffer contribution).

Hold time & droop - off leakage & capacitances - minimum
VT corner and maximum temperature, worst case common-mode
voltages are where you should look

Charge injection - symmetry and control of switch overdrive &
timing skews

In an "exercise" you may not have all of these supplied
to you, but they may be derivable from other figures
of merit, system clock timing etc. For example with a 1MHz
clock sampling on one phase and converting on another,
you might make up a hold/droop requirement saying
<1LSB droop (V=?) in 500nS (the hold window). Then the
Chold*dV/dt is your total allowed Ileak (from all contributors,
not just the switch(es)).

Input settling to <1LSB within the opposite 500nS may also
be figured - with the number of bits, 1/2^n can tell you how
many time constants as e^(-t/tau), then look at Ron*Chold
as being less than that in order for a full scale step to be
tracked in the allotted time slot.

Sample speed driven Ron and hold time driven Ioff define
your "box" pretty much.
 

    E

    eegchen

    Points: 2
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hi dick_freebird,

That's very helpful. Thanks a lot.


dick_freebird said:
This is part of your job as a designer, to turn pin electricals
into block, component level requirements for your design.

In the case of the switch, as part of a sample/hold, you
probably have several concerns.

Input settling time - on resistance and the self- and explicit
hold capacitance give your time constant (presuming
no buffer contribution).

Hold time & droop - off leakage & capacitances - minimum
VT corner and maximum temperature, worst case common-mode
voltages are where you should look

Charge injection - symmetry and control of switch overdrive &
timing skews

In an "exercise" you may not have all of these supplied
to you, but they may be derivable from other figures
of merit, system clock timing etc. For example with a 1MHz
clock sampling on one phase and converting on another,
you might make up a hold/droop requirement saying
<1LSB droop (V=?) in 500nS (the hold window). Then the
Chold*dV/dt is your total allowed Ileak (from all contributors,
not just the switch(es)).

Input settling to <1LSB within the opposite 500nS may also
be figured - with the number of bits, 1/2^n can tell you how
many time constants as e^(-t/tau), then look at Ron*Chold
as being less than that in order for a full scale step to be
tracked in the allotted time slot.

Sample speed driven Ron and hold time driven Ioff define
your "box" pretty much.
Click to expand...
 

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