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multi cycle path - atspeed test

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abc_81

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atspeed test querries

Please explain the meaning of multi cycle path, and how do we deal with them in the atspeed test ? How multicycle paths affect the coverage values ?
 

Re: atspeed test querries

At Speed test uses two high speed functional clock pulse to test the delay of the combinational lgoic between registers. However, some combinational logic will take more than one cylce to propagate. So the two clock pulses are not enough for these logic.
usually, we will set false paht of these paths. Another way is to use pipelineing to make the multi-cycles work as one cycle path.
thanks!
 
transition and path delay

If the coverage of the transition faults if high enough, does that mean we need not go for path delay test? or is it that path delay selection depends on the number of clock domains or IDDQ results or frequency of the design ?
 

Usually, the path dealy test selection is based on the timing analysis.
We will often choose the most critical timing path under path delay test.
 

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