Setup/Hold after the ASIC tapeout

Hi All

This is an interesting question that I Came across in an interview process..

I was asked that when the ASIC is taped out and it is in lab to test you figure out that it is not working fine. Now it is not a logical fault but some sort of metastability issue.

Q1. How can you figure out that it is a settup time /Hold time violation .

Q2. In the case of setup time violation you can slow down the frequency and make it run but what are the other ways to make it run or avoid setup time violation apart from increasing the clock width.

Q3 Now you have only Taped out ASIC and you figure out that some pileline is not working fine even after slowing the frequency how will you handle it.

Though I was confused that how one can know that the pile line is the culprit as you cannot access the core realtime

I will appreciate answers from all

Thanks

vips

I think We can change the phase of the clock to make it workable apart from increasing the clock width.

Adjust the voltage and/or temperature.