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how to eliminate "assign" in verilog netlist?

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meshell

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Hi,
Does anyone know how to eliminate the "assign"sentence in verilog netlist using tools like Design Complier?
Thanks a lot.

Regards,
Meshell
 

For Design compiler...

##
## Run after elaboration
##
set_fix_multiple_port_nets -all -buffer_constants
set verilogout_equation false
set verilogout_no_tri true
set write_name_nets_same_as_ports true
set verilogout_higher_designs_first false
set verilogout_show_unconnected_pins true
set hdlout_internal_busses true
set_fix_multiple_port_nets -all [get_designs]
set current_design digitalTop

##
## To write out netlist
##
change_names -rules verilog -hierarchy
write -format verilog -hier -output digitalTop.v
 

Dear I dont know about DC but in encounter we do like this:-

Encounter removes assign statements and does not change the netlist. Use the following command:
setDoAssign off


 Encounter removes assign statements by merging the nets in Assign statements,
changing the netlist. Use the following command:
setDoAssign on

 Encounter replaces Assign statement with buffers during design import. Use the
following command:
setDoAssign on -buffer buffer_cell
 
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