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Two Stage CMOS Op Amp Simulation Setup

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jediknight2001

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Hi,
I am designing a 2 stage CMOS Op Amp to meet a certain specs for my class. However, I am not sure I am understand how to set up the simulation. Attached is the simulation set up from Sedra's Microelectronics Circuits. Can any one explain briefly the setup for me, and what should I do to show:
1. Input Common Mode Rage
2. Output Swing
3. DC open loop gain

Can you suggest any other simulation set up? My teacher suggest using the circuit with "really" big L and C because in this set up i have to worry about offset voltage?

Thanks,
 

Can you suggest any other simulation set up? My teacher suggest using the circuit with "really" big L and C because in this set up i have to worry about offset voltage?


How could we know if you have to worry about offset or not ?
It simply depends on your design and layout.
To measure gain and voltage swing you need an operational point in the middle of the linear gain range.
Therefore, why don´t you check if this condition is met or not?
Then you will know, if you have to worry about offset.
 

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