Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Increasing/decreasing the rise time of signal on differential trace

Status
Not open for further replies.
zeshan102

zeshan102

Advanced Member level 4
Joined
May 31, 2003
Messages
100
Helped
11
Reputation
22
Reaction score
8
Trophy points
1,298
Location
Heart of Pakistan
Activity points
649
sorry I want to decrease the rise time of signal on differential trace is there any trick i can play with layout to increase it
 

Re: increase Rise time

I am not very sure why you want to increase rather than decrease the rise time.But if you really want to, then some basic troubles in signal integrity maybe really give you some help.(sounds really ridiculous)
 

Re: increase Rise time

during compliance test chip fails because of very high edge rate of 1.7 V/ns Is there any posssibility to reduce the edge rate by changing the layout of differential pair
 

increase Rise time

Parameters involved in the problem are transmitter waveform and impedance, transmission line impedance and
receiver impedance. Typically, a matched differential pair would be expected to reproduce (more or less exactly)
the transmitted waveform. It's hard to guess the actual problem from your post.
 

Re: increase Rise time

the problem is measurement shows risetime higher than expected is there anyway to reduce this risetime by changing only inthe layout of diff trace
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top