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multi Vdd design techniques

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sudheerprasad

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hi all,
i have two cell libraries one characterized at 1.8v ,a nd the other at .4v.
i want to use them in multi vdd design technique.how i can i use two libraries at a time,should i do any changes in the RTL verilog code??
where should i specify that a block operates at a particular voltage,
if any body have tutorials or stuff related multi vdd techniques plz post them

thanx
sudheer
 

Hi,


For this, in back end, especiaaly in encounter tool, you should specify power domains. So the tool will display two areas to place and route them separately dependingon multi supply voltages.
Regards,
K.Viswanadh Babu
 

Hi,
i suggest you started studying the CPF flow. Here is a link which helps:
https://www.si2.org/?page=907
In any case, if you dont want to change your RTL you can just specify
two instace groups, one for the .4 and one for the .8. Then create two
power domains and associate each instance group with its corresponding
power domain. These steps should be prepared before backend and after
synthesis, by creating a .cpf file which will be loaded during the initial steps
of the backend using loadCPF, commitCPF etc. etc.

pmat
 

Hi,

Refer Low power methodology manual from synopsys for the design.

Thanks..

HAK..
 

sudheerprasad said:
hi all,
i have two cell libraries one characterized at 1.8v ,a nd the other at .4v.
i want to use them in multi vdd design technique.how i can i use two libraries at a time,should i do any changes in the RTL verilog code??
where should i specify that a block operates at a particular voltage,
if any body have tutorials or stuff related multi vdd techniques plz post them

thanx
sudheer
Click to expand...

There are already some mature books talking about your topic. Yet, we need to rethink this topic from native silicon operations. Common methods are putting long datapath (critical timing path ALU/MAC logics) in high VDD area and short datapath (control logics) in low VDD area. Logic modules are finally turned into physical layouts so it is better to handle them by module. In this way, backend guys could just generate voltage areas accoring to your logic partition, distribute high/low power and pay attention to signal level shifts when crossing the voltage area boundary.
 

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