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multiply accumulator in vhdl help needed

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saraiust

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multiply accumulator

hi everybody,

I need to make a multiply accumulator in vhdl and i dont have any idea..
can you help me to find an architecture for multiply accumulato with simple gates, like and,nand,or... --asap--
i mean a simple architecture to understand how to simulate that.

thanks!
 

i want that too please but without using (*)
 

I need to make a multiply accumulator in vhdl and i dont have any idea..
Click to expand...

As I understand you have 2 inputs and want to MAC

you should implemennt this simple algorithm:

out_next = in1 * in2 + out;

The following simple module can do that:
Code: 
module mac (in1, in2, out, clk, init);

input clk, init;
input [7:0] in1, in2;
output reg [31:0] out;

wire [15:0] mult_res;

assign mult_res = in1*in2;

always @(posedge clk) begin

  if (init) begin
    out <=  mult_res;
  end else begin
    out <=  mult_res + out;
  end

end

endmodule



i want that too please but without using (*)
Click to expand...

There are a lot of different multiplication algorithms. It depends on your needs. You can choose 1 cycle, multy cycles or pipelined.


Bests,
Syswip
http://syswip.com/
 

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