Latching Analog Voltage - sample and Hold

Latching Analog Voltage

Dear All,

I am working on a project where I need to latch the analog voltage. In this there are 6 amplifiers which requires 0-10V varriable voltages and all should be latched on desire levels until we don't change. The microcontroller is working on time sharing having too many Inputs and outputs. So I need an analog latch for the same. Please let me know if someone have some idea for the same.

Thanks'

Vicky

Latching Analog Voltage

Your apparently refering to a Sample & Circuit. It can be basically built from an analog switch, a capacitor and a buffer OP.

until we don't change.

Click to expand...

doesn't seem a clear condition, however.

Re: Latching Analog Voltage

Dear Sir,

The voltage level is not fix all times. It needs to be modified frequently. I am using a DAC connected to micro and after it there is 4051 to share outputs in 6 stages.

Vicky

Re: Latching Analog Voltage

I am using a DAC connected to micro and after it there is 4051 to share outputs in 6 stages.

Click to expand...

That's if fact a kind of S&H circuit. The same can be done for input signals.

So what are you actually asking for?

Re: Latching Analog Voltage

I want to latch the voltage level on all 6 stages where 4051 is connected.

Vicky

Latching Analog Voltage

Sample & hold, aka track & hold amplifier. You can do a
"poor man's" S/H with op amp and CMOS switches, or you
can find them with the op amps in most analog IC mfrs'
lineup.

However, S/H amps have a finite droop rate (worse w/
temperature and so on). If you are creating these voltages
with a micro & DAC, then probably what you want is to have
a set of registers each with their own DAC. A good S/H amp
may be more expensive than octal latches and DACs.

If this is on the input side then you either want N S/H and
a N:1 mux, to drive a single ADC input channel, or put the
S/H after the mux if you have enough sample interval
(settling time) in your cycle.

The slower you want to run, the more error you will pick up
in the S/H area from the droop rate. In app notes you
should find some guidelines for low-leakage PCB layout,
signal guards and so on (the PCB may be worse for leakage
than the IC elements themselves).