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Question about inverter design

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k1gunner

k1gunner

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Hello

I have a question about inverter design.
When designing inverter, usually (W/L)p is bigger than (W/L)n twice.
I know that's why kp is smaller than kn around 1/2.

When I extract kp,kn from my design model (0.18um),
it is kn=157u A/V^2 , kp=42u A/V^2.
Can I make a ratio (W/L)p and (W/L)n is 4:1 ?
in my case, which is right decision? 2:1 ? 4:1?
thanks in adv.
 

Hi,

If you are looking for perfectly balanced rise/fall time (Tr/Tf), then pmos to nmos ratio should be equal to kn/kp.

If the inverter is required for very low frequency operation, I do not think you really need to match Tr/Tf, the reason being, period is very large compared to Tr/Tf. Then, you can save lot of area.
It is the compromise between the two.

Regards,
Raviprasad K
 

If you want a balanced tf and tr, you should sized up the inverter in such that you get logic threshold VDD/2. For hand calculation you can use ratio 4:1. To get the exact value then run dc sweep and adjust you W accordingly. Increasing W will increase your switching current and also capacitance. It is better to keep minimum size while mantain balanced logic threshold.
 

Hello,

I have a question. I don understand the correlation between balancing tr and tf and equalling (w/l)p/(w/l)n with kn/kp. Can you please explain??

thanks in advance.
 

Tf=0.7RnCout where Rn=[2VDD/UnCox(VDD-Vtn)2 X [L/W]
Tr=0.7RpCout where Rp=[2VDD/UnCox(VDD-Vtp)2 X [L/W]

Cout=Cox*Ln*Wn + Cox*Lp*Wp
 

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