dtzounakos
Member level 3
Hi!
I want to design the classic CMOS omp amplifier with two stages (n - channel differential pair for 1st stage and p - channel the common source stage) using theGm/IDS methodology. I want someone to tell me if the following design steps are correctly in order to obtain the DC conditions.
We know that the analog ground (DC BIAS) at input and output terminals is VDD/2! (Vss=0)
Using specifications such as: a)Slew Rate
b)Z>10Ωτ
c) Cc=something
d)CL=something
i obtain gm1_2,gm_5(this is the transconductance of pmos common source), Ibias (the bias current of first stage), I5 (the bias current of second stage)
Now, in order to obtain the (W/L) of each transistor, i use gm/ids vs IDS/(W/L) methodology.
I start my design, creating a standalone transistor circuit in Cadence enviroment. (eg. the PMOS of second stage alone,not with the bias transistor of second stage). My question is: Should we bias the PMOS transistor with same known bias values of Miller OTA?
For instance, i bias the terminals of PMOS transistor with these values: Vs=VDD, Vd=VDD/2 and Vg=this is the sweep variable and i plot the gmoverid vs ids/(W/L) graph. I found the corresponding W/L and Vov, so Vg of the PMOS transistor. So far, is this a right design concept?
And next, having found Vg(DC BIAS) which is equal with Vd1,2 of differantial pair, i again create a new standalone transistor NMOS to plot gmoverid vs IDS(W/L) graph. Now the DC BIAS terminals are: Vd1=Vg(pmos of second stage), Vg1=VDD/2 and Vs=DC Sweep variable at spectre simulator! Is it right?
Here, i upload the above circuits:
I will appreciate if someone would like to answer (if he/she knows) my questions, and not to tell me visit this page,download this book,or read this/these papers(such as Jesper's). I want a specific answer. I want someone to tell me if this approach (respect with DC Bias of standalone transistors and their relationship with Miller OTA circuit) is realistic!
Thanks a lot and sorry for writing a novel!!
I want to design the classic CMOS omp amplifier with two stages (n - channel differential pair for 1st stage and p - channel the common source stage) using theGm/IDS methodology. I want someone to tell me if the following design steps are correctly in order to obtain the DC conditions.
We know that the analog ground (DC BIAS) at input and output terminals is VDD/2! (Vss=0)
Using specifications such as: a)Slew Rate
b)Z>10Ωτ
c) Cc=something
d)CL=something
i obtain gm1_2,gm_5(this is the transconductance of pmos common source), Ibias (the bias current of first stage), I5 (the bias current of second stage)
Now, in order to obtain the (W/L) of each transistor, i use gm/ids vs IDS/(W/L) methodology.
I start my design, creating a standalone transistor circuit in Cadence enviroment. (eg. the PMOS of second stage alone,not with the bias transistor of second stage). My question is: Should we bias the PMOS transistor with same known bias values of Miller OTA?
For instance, i bias the terminals of PMOS transistor with these values: Vs=VDD, Vd=VDD/2 and Vg=this is the sweep variable and i plot the gmoverid vs ids/(W/L) graph. I found the corresponding W/L and Vov, so Vg of the PMOS transistor. So far, is this a right design concept?
And next, having found Vg(DC BIAS) which is equal with Vd1,2 of differantial pair, i again create a new standalone transistor NMOS to plot gmoverid vs IDS(W/L) graph. Now the DC BIAS terminals are: Vd1=Vg(pmos of second stage), Vg1=VDD/2 and Vs=DC Sweep variable at spectre simulator! Is it right?
Here, i upload the above circuits:
I will appreciate if someone would like to answer (if he/she knows) my questions, and not to tell me visit this page,download this book,or read this/these papers(such as Jesper's). I want a specific answer. I want someone to tell me if this approach (respect with DC Bias of standalone transistors and their relationship with Miller OTA circuit) is realistic!
Thanks a lot and sorry for writing a novel!!