fencl
Member level 1
after tape out, one chip's pll is 'out of work' sometimes.
for eg. fin=35M/s, fout=280M/s,my pll is simple with pd,chp,vco,and 1/8 devider for comparation with fin, even without lock check circuit. I can test ck_out by 1/4 divider. that is 70M/s, sometimes it is well meet, sometimes it will go to 60M/s. each times i power up, 90% will be 60M/s,10% will be 70M/s.and only one chip in many chips have this problem.
i use some way connect this bad chip fin to other pll for input ,it's work well. and other chip fin to this pll for input.still the same bad case.
what problem is it ? need help sincerely!
for eg. fin=35M/s, fout=280M/s,my pll is simple with pd,chp,vco,and 1/8 devider for comparation with fin, even without lock check circuit. I can test ck_out by 1/4 divider. that is 70M/s, sometimes it is well meet, sometimes it will go to 60M/s. each times i power up, 90% will be 60M/s,10% will be 70M/s.and only one chip in many chips have this problem.
i use some way connect this bad chip fin to other pll for input ,it's work well. and other chip fin to this pll for input.still the same bad case.
what problem is it ? need help sincerely!
