How to decide the min Vdd to a CMOS op Amp?

Hi , every one,

I have a question about how to design and analyse a op Amp( or any other circuit)´s min Vdd.

I think the basic idea for the min Vdd is it need to let each transistor in a branch "on", that will be Vgs > Vth, right?

so, take a inverter stage for example, then the Vdd min should be (Vthp +Vthn), right?

but in op Amp design, how to make sure a op Amp can working on the idea min Vdd, what other thing will cause the actual min Vdd increasing ? how to determine the margin for the Vdd range?

Thank you !

You'd really want to run a series (w/ process corners,
as VTN and VTP dominate the result) and criticize all of the
usual results, against their "datasheet" limits. Min VDD
for the user, is where it's no longer giving the performance
they need.

You can operate subthreshold if you design for it and can
take the performance hit. You could get to below max(VTN,VTP)
with a low stack height, very low current etc. although
this is not likely to be a very high quality op amp in terms
of gain, CMRR/PSRR etc.

Thank you very much for your reply,

seems a bit hard to me....

do you mean: the design parameters that effecting the min Vdd for a op amp are Vth?
but need to check with the corner situation?

other wise, if the Vdd is lower a bit more ( from satisfy all transistor to above Vth), then , at the design step, need to design transistors to working at subthreshold, right?

do I get what your mean ?

So, basicly, at the beginning of design, and I was gave a specification of a min Vdd,
then I just need to do all calculation on this min Vdd as operating point, right?

is it always have some way to fullfill the required min Vdd?
Or, normally , on the other hand, ---- do design first, fullfill other spec ( gain , BW, SR...) and then sweep the Vdd to see how min the Vdd could be?

Than you !!