# verilog code for 4-bit counter with JK flipflop

1. ## verilog code for 4-bit counter with JK flipflop

hello
A verilog code for 4-bit up/down counter with jk flipflop that counts with step of 3,it means that it counts 0-3-6-9-12-15.
I know this problem has got a very easy answer without using JK ff,but i just want to know the answer using JK flipflps.
thanx

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2. ## Re: verilog code for 4-bit counter with JK flipflop

I can write the verilog code for JK ff,it is easy!;) My problem is that I don't know how to write the code, with the step of 3, and I don't know how to make 4 jk ff count this string;0,3,6,9,12,13.

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3. ## Re: verilog code for 4-bit counter with JK flipflop

Use the JK flip flop excitation table and draw up your circuit excitation table with your present and next states. Use Karnaugh maps to solve for your J and K values for each flip flop. Once you have this it will be fairly easy to code in verilog. Instantiate your JK flip flop and your J and K values for each flip flop will be combination circuits of your four bit input to the counter.

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4. ## Re: verilog code for 4-bit counter with JK flipflop

can you give the code for the counter using jk flip flop

5. ## Re: verilog code for 4-bit counter with JK flipflop

You can create a normal 3 bit counter(MOD 6 counter) using JK flipflops and then get the required count values using combinational logic.
The counter should reset when the count value reaches 5.
Now write a combinational logic for the following conversion.
000 -> 0000
001 -> 0011
010 -> 0110
011 -> 1001
100 -> 1100
101 -> 1111

This is how you should design counters with random count sequences. If you have some seq like 10,400,62,2,7,10,400,62,2,7,...etc then you dont need 9 FF's. Just 3 FF's will do.Because only 5 states are there.

This is a code for 4 bit counter using JK flip flops.
VHDL coding tips and tricks: 4 bit Synchronous UP counter(with reset) using JK flip-flops

--vipin
VHDL coding tips and tricks

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6. ## Re: verilog code for 4-bit counter with JK flipflop

can you give the code in verilog.. i dont know vhdl

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