---
+ Post New Thread
Results 1 to 6 of 6
  1. #1
    Newbie level 4
    Points: 630, Level: 5

    Join Date
    Sep 2009
    Location
    Iran
    Posts
    7
    Helped
    1 / 1
    Points
    630
    Level
    5

    verilog code for 4-bit counter with JK flipflop

    hello
    can any one please help me with this problem:
    A verilog code for 4-bit up/down counter with jk flipflop that counts with step of 3,it means that it counts 0-3-6-9-12-15.
    I know this problem has got a very easy answer without using JK ff,but i just want to know the answer using JK flipflps.
    thanx

    •   Alt23rd October 2009, 23:41

      advertising

        
       

  2. #2
    Newbie level 4
    Points: 630, Level: 5

    Join Date
    Sep 2009
    Location
    Iran
    Posts
    7
    Helped
    1 / 1
    Points
    630
    Level
    5

    Re: verilog code for 4-bit counter with JK flipflop

    I can write the verilog code for JK ff,it is easy!;) My problem is that I don't know how to write the code, with the step of 3, and I don't know how to make 4 jk ff count this string;0,3,6,9,12,13.


    1 members found this post helpful.

    •   Alt26th October 2009, 15:31

      advertising

        
       

  3. #3
    Junior Member level 3
    Points: 1,454, Level: 8

    Join Date
    Apr 2006
    Posts
    31
    Helped
    6 / 6
    Points
    1,454
    Level
    8

    Re: verilog code for 4-bit counter with JK flipflop

    Use the JK flip flop excitation table and draw up your circuit excitation table with your present and next states. Use Karnaugh maps to solve for your J and K values for each flip flop. Once you have this it will be fairly easy to code in verilog. Instantiate your JK flip flop and your J and K values for each flip flop will be combination circuits of your four bit input to the counter.


    1 members found this post helpful.

    •   Alt26th October 2009, 18:33

      advertising

        
       

  4. #4
    Newbie level 3
    Points: 400, Level: 4

    Join Date
    Oct 2010
    Posts
    3
    Helped
    0 / 0
    Points
    400
    Level
    4

    Re: verilog code for 4-bit counter with JK flipflop

    can you give the code for the counter using jk flip flop



  5. #5
    Full Member level 6
    Points: 2,704, Level: 12
    vipinlal's Avatar
    Join Date
    Mar 2010
    Location
    India
    Posts
    349
    Helped
    76 / 76
    Points
    2,704
    Level
    12

    Re: verilog code for 4-bit counter with JK flipflop

    You can create a normal 3 bit counter(MOD 6 counter) using JK flipflops and then get the required count values using combinational logic.
    The counter should reset when the count value reaches 5.
    Now write a combinational logic for the following conversion.
    000 -> 0000
    001 -> 0011
    010 -> 0110
    011 -> 1001
    100 -> 1100
    101 -> 1111

    This is how you should design counters with random count sequences. If you have some seq like 10,400,62,2,7,10,400,62,2,7,...etc then you dont need 9 FF's. Just 3 FF's will do.Because only 5 states are there.

    This is a code for 4 bit counter using JK flip flops.
    VHDL coding tips and tricks: 4 bit Synchronous UP counter(with reset) using JK flip-flops

    --vipin
    VHDL coding tips and tricks
    Last edited by vipinlal; 16th October 2010 at 19:31. Reason: forgot to attach link



  6. #6
    Newbie level 3
    Points: 400, Level: 4

    Join Date
    Oct 2010
    Posts
    3
    Helped
    0 / 0
    Points
    400
    Level
    4

    Re: verilog code for 4-bit counter with JK flipflop

    can you give the code in verilog.. i dont know vhdl



+ Post New Thread
Please login