AdvaRes
Advanced Member level 4
Hi,
I have asynchronous wrapper (spice netlist annotated). This comonent have a lot of I/O and Spectre simulation is very complex because I fed inputs with vsources for digital simulation. There is a lot of inputs and the signals are very complex to generate using Vpulse. Also simulation last 10 Hrs !!!
How can I use VHDL testbench containing the digital inputs for the spice model and cosimulate VHDL and spice ?
Which tool support that ?
I have asynchronous wrapper (spice netlist annotated). This comonent have a lot of I/O and Spectre simulation is very complex because I fed inputs with vsources for digital simulation. There is a lot of inputs and the signals are very complex to generate using Vpulse. Also simulation last 10 Hrs !!!
How can I use VHDL testbench containing the digital inputs for the spice model and cosimulate VHDL and spice ?
Which tool support that ?
