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How to deal with the internal clock during DFT

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ada86831

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Hi, all,
There is an internal clock generated by the system clock. When I inserted scan chain, all the flip-flops driven by the internal clock weren't in the scan chain. It said the CK of these FF are uncontrolled. I set mixing_clock mix_clocks.
How can i fix those problems?

Thank you so much.
 

You need to by pass this generated clock using MUX. MUX can be inserted in design itself or now-a-days tool can also insert MUX automatically by finding such places. But definetely, second option is not receommended to be used as it may create equivalance issues.

MUX whose input 1 would be your generated clock, input 2 would be your top level main clock and select signal wuld be test_mode. so when u r in testing mode, you bypass generated clock and pass on top level main clock to all flops and when you are in functional mode you supply actual generated clock ..

hope i was clear ...
 

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