Qn on synthesis of "default" branch in case statem

All,

I have a question on the "default" branch in a Verilog case
statement. Notice that the following case statement features all
outcomes for the case variable "encoded_signal". There is also a
default statement.


always @ (encoded_signal)
begin
case(encoded_signal)
3'b000: decoded_out = 8'b00000000;
3'b001: decoded_out = 8'b00000001;
3'b010: decoded_out = 8'b00000011;
3'b011: decoded_out = 8'b00000111;
3'b100: decoded_out = 8'b00001111;
3'b101: decoded_out = 8'b00011111;
3'b110: decoded_out = 8'b00111111;
3'b111: decoded_out = 8'b01111111;
default: decoded_out = 8'b11111111;
endcase
end


Since every valid outcome for "encoded_signal" is already accounted
for, will the synthesis tool synthesize the default statement? And if
so how?


Could this lead to redundant logic in the synthesized design?


Regards,
animotion

Unless causing a syntax error, it would lead to nothing.

Re: Qn on synthesis of "default" branch in case st

This is considered as "full_case" and default will not be synthesized .