kickbeer
Full Member level 3
glitch digital logic
Hi,
I've just simulated a folding & interpolating ADC and found a glitch around 0.5 V after an EX-OR logic in my digital part. In the attachment, V(c07) and V(c23) are the input and V(out_07_23) is the output of EX-OR. As you can see in waveform, there is a glitch of 0.5 V(at time 0.3 us) of the output of EX-OR.I'm wondering how this happened because both the inputs travel at the same speed. How to get rid of this problem? I've been working on this since two days.
Hi,
I've just simulated a folding & interpolating ADC and found a glitch around 0.5 V after an EX-OR logic in my digital part. In the attachment, V(c07) and V(c23) are the input and V(out_07_23) is the output of EX-OR. As you can see in waveform, there is a glitch of 0.5 V(at time 0.3 us) of the output of EX-OR.I'm wondering how this happened because both the inputs travel at the same speed. How to get rid of this problem? I've been working on this since two days.