averros
Newbie level 2
Hi,
I'd like to simulate TFT analog circuits using Cadence. I have not been able to find much information about TFT process support in Cadence tools. Does anyone have any experience with this?
Basically, I'd like to see (and implement) the full flow of analog TFT design:
- schematic creation in Virtuoso
- Simulation with Spectre and Ultrasim (using the latest RPI models)
- layout with Virtuoso
- DRC, LVS, ... etc with Virtuoso
- parasitic extraction with Assura
- Back-annotation with Assura
-Post extraction simulation
So far, I've seen brochures outlining this kind of flow in Silvaco's Simucad tools. I haven't found anything similar for Cadence which is my preferred tool set. Any suggestions?
Thanks.
Added after 8 minutes:
This is the info from Silvaco that I was referring to:
**broken link removed**
Thanks.
I'd like to simulate TFT analog circuits using Cadence. I have not been able to find much information about TFT process support in Cadence tools. Does anyone have any experience with this?
Basically, I'd like to see (and implement) the full flow of analog TFT design:
- schematic creation in Virtuoso
- Simulation with Spectre and Ultrasim (using the latest RPI models)
- layout with Virtuoso
- DRC, LVS, ... etc with Virtuoso
- parasitic extraction with Assura
- Back-annotation with Assura
-Post extraction simulation
So far, I've seen brochures outlining this kind of flow in Silvaco's Simucad tools. I haven't found anything similar for Cadence which is my preferred tool set. Any suggestions?
Thanks.
Added after 8 minutes:
This is the info from Silvaco that I was referring to:
**broken link removed**
Thanks.