ctzw
Newbie level 2
set_scan_signal
I learnt from all the Synopsys DFT tutorials that when doing scan insertion, 'set_scan_signal' can be used. However, I found my dc_shell-t could not recognize this command:
dc_shell> help set_scan_signal
Information: No commands matched 'set_scan_signal'. (CMD-040)
I was using:
dc_shell version - A-2007.12-SP5
dc_shell build date - Jul 18, 2008
So I used set_dft_signal instead, which is supposed to work in Autofix mode. It worked somehow. My DFT scritp contains following commands( the scan style is multiplexed_flip_flop):
1)
set_dft_signal -view exist -type ScanClock -timing [list 45 55] -port [get_ports CK] ; CK is the clock input port in top design RTL code.
2)
set_dft_signal -view exist -type Reset -port [get_ports rst_i] -active_state 1; rst_i is the reset input port in top design RTL code
3)
create_port -direction "in" scan_enable
set_dft_signal -view spec -type ScanEnable -active 1 -port scan_enable
However, I got hundreds of test rule violations when doing dft_drc, saying:
Warning: Reset input RN of DFF wbs_vtim_reg_20_ was not controlled. (D3-252)
How can I eliminate such violations, since I have defined rst_i in top module as the reset port. But I am not sure whether there are other reset inputs as well that I have missed. I was doing synthesis on a design with 100K gates.
Thanks.
I learnt from all the Synopsys DFT tutorials that when doing scan insertion, 'set_scan_signal' can be used. However, I found my dc_shell-t could not recognize this command:
dc_shell> help set_scan_signal
Information: No commands matched 'set_scan_signal'. (CMD-040)
I was using:
dc_shell version - A-2007.12-SP5
dc_shell build date - Jul 18, 2008
So I used set_dft_signal instead, which is supposed to work in Autofix mode. It worked somehow. My DFT scritp contains following commands( the scan style is multiplexed_flip_flop):
1)
set_dft_signal -view exist -type ScanClock -timing [list 45 55] -port [get_ports CK] ; CK is the clock input port in top design RTL code.
2)
set_dft_signal -view exist -type Reset -port [get_ports rst_i] -active_state 1; rst_i is the reset input port in top design RTL code
3)
create_port -direction "in" scan_enable
set_dft_signal -view spec -type ScanEnable -active 1 -port scan_enable
However, I got hundreds of test rule violations when doing dft_drc, saying:
Warning: Reset input RN of DFF wbs_vtim_reg_20_ was not controlled. (D3-252)
How can I eliminate such violations, since I have defined rst_i in top module as the reset port. But I am not sure whether there are other reset inputs as well that I have missed. I was doing synthesis on a design with 100K gates.
Thanks.