ars-vita
Newbie level 1
when inside process + vhdl
Hi everybody!
Does somebody has any idea concerning the following question: how will it influence the result design if I take combinational logic out of the clocked process? What are the differences in synthesis?
Compare the following two implementations of count register as an example.
1st implementation with the addition inside the clocked process:
2nd implementation with the addition out of the process:
Hi everybody!
Does somebody has any idea concerning the following question: how will it influence the result design if I take combinational logic out of the clocked process? What are the differences in synthesis?
Compare the following two implementations of count register as an example.
1st implementation with the addition inside the clocked process:
Code:
process (CLK, nRESET)
begin
if nRESET = '0' then
COUNT <= (others => '0');
elsif CLK'event and CLK = '1' then
if ENABLE = '1' then
COUNT <= COUNT + 1;
end if;
end if;
end process;2nd implementation with the addition out of the process:
Code:
COUNT_TMP <= COUNT + 1 when ENABLE = '1' else COUNT;
process (CLK, nRESET)
begin
if nRESET = '0' then
COUNT <= (others => '0');
elsif CLK'event and CLK = '1' then
COUNT <= COUNT_TMP;
end if;
end process;