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  1. #1
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    question about standard cell library

    hi

    can anyone tell me which cell should we include in a cell library?

    thanks
    Elika

    •   Alt8th September 2009, 07:01

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    Re: question about standard cell library

    Hi,
    Normally standard cells would have buffers, INV, AND, OR, NAND, AOI (AND-OR-INV), MUX, flip-flops, etc, etc.
    Are you creating your own library from scratch? If you have a bunch of cells lying around (now how does that happen?) & don't know how to group them, I think you should put everything according to technology.
    If you are trying to do some admin work whether on paper or on a database, well, there's no fixed definition of what has to be in a standard cell library - AFAIK. Just look at the types of standard cells from any foundry & you'll see there are loads you can find in one alone.
    But if you have some sort of vlsi assignment to do I'll say the ones I mention would be ok for a start... and good luck finishing them.



    •   Alt8th September 2009, 08:32

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    question about standard cell library

    hi cop02ia
    thanks for your answer
    first of all,I want to apology for my bad english speaking.
    i'm working in a new company as a designer.they wanted me to publish a library of standard cells.and i don't know from where I must start!
    what you just mentioned in your first line,is what I use to see in any article!
    would you please explain more about the standard cell library?

    GOOD LUCK



    •   Alt14th September 2009, 09:24

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  4. #4
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    Re: question about standard cell library

    Hey hi,

    A Standard lib contains a complete list of cells as already mentioned.
    All these cells are defined as timing models, written in such a way that a synthesizer can understand.

    In order to build a lib, first you need to make layout of all the cells that you plan to include in the lib.

    For example: Half adder:
    You will have to build half adders for different drive strengths.

    NAND gates:
    You will have to build NAND gates for 2 3 4 inputs all having differnt drive strengths.

    Drive strength usually increase exponentially (X4 X8 X16 X32 ... ths is not the usual trend but this is what I have seen till now).

    By drive strength one means: How big is your fanout in comparison to the unit transistor.
    For example:
    Drive strength X4 means: The cell has a driving capacity or fanout which is 4 times that of a unit cell fanout which is uslally 4. So your cell can drive 16 unit inverters.

    After sizing has been done, you need to start charactizing the cells for setup, hold power delay.

    Now you will need specification under which there parameters need to be measured. Now those specification are company specific, meaning what load slew rates etc under which certain properties are to be measured.

    Further these specification alter for the type of cell you have.
    For example: If you have a flip flop then the measuring constraints are different as compared to a AND gate.

    I prefer using HSPICE for characterization.
    You will have to go learn how to write Test benches in HSPICE. This will enable you to measure power, delay setup and holds time.

    Setup hold times are easy to measure but power is a bit tricky. Power need to be measured for iput output and clock if you have one.

    There is something like fall power rise power fall, all these specification needs to be provided to you by your firm.

    Hope this helps.

    Tell me if yu have more questions.

    Thanks
    Saurabh



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