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question about 1.5b/stage pipeline ADC

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henrywent

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adc 1.5bit

Hi, there,
As is well known, the comparators in the sub-ADCs of a 1.5b/stage pipeline ADC can tolerate offset error as large as Vref/4, but why is it that ? can someone explain in more detail or post some links here, thanks!

Added after 16 minutes:

AND I also want to know which is the FIRST paper dealing with 1.5 bit-per-stage pipeline ADC ? thanks!
 

number of stage adc pipeline

Dear Henrywent
You know that each comparator in an ADC can stand an error about LSB/2 and in a 1.5bit(or 2 bit) LSB/2 is equal Vref/4.
 

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    henrywent

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u can use this paper.

"S. Lewis, P. R. Gray, “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuits, Vol. 22, No. 6, pp. 954-961, Dec. 1987."
 

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