vhdl logic_vector to signed int conversion

vhdl logic_vector

I wish to take a 16-bit logic vector in (from an ADC). This is an AC-biased sine wave connected to an ADC centered around the mid point of the ADC (i.e. 32767).

How do I change this to a signed integer that i then use to do a multiply and subsequently output as a signed logic vector?

I have some code snipets below,

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Library IEEE;
Use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
use IEEE.Std_Logic_signed.all;

DAT_I : in std_logic_vector(15 downto 0);
DAT_O : out std_logic_vector(15 downto 0);

signal A_int: integer range -2147483647 to 2147483647;
signal result_int: integer range -2147483647 to 2147483647;


A_int <= conv_integer(DAT_I);

Result_int <= (A_int-32767) * coef_int; -- convert A to signed 16-bit and multiply

DAT_O(15 downto 0) <= conv_std_logic_vector(result_int,16);

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does the above give me a signed DAT_O?

Do I need to replace the following?

A_int <= conv_integer(unsigned(DAT_I));

signed int range

- The conversion from "offset binary" to two's complement is done by inverting the MSB (respectively performing XOR x"8000") rather than substracting -32767. You can check, that the latter produces an overflow for full scale input of x"FFFF".

- The multiply result has 16 + coef_int'length bits, so you can't use it for an 16 bit output without causing truncation. You should rather select 16 bits from the left. If coef_int is a signed signal, you get two sign bits in result. You must use saturation logic to scale the result to the full signed range.