Register is illegal in left-hand side?? What happend?

illegal left hand side of continuous assign

Hi all,

I am using Verilog to design a system.

But there is an error in my code.
//--------------------------the error info------------------------------
"Register is illegal in left-hand side of continuous assignment"
//------------------------------------------------------------------------

//---------------------------my code-----------------------------------

reg [31:0] trigger;
reg [3:0] triggerinput[7:0];
assign trigger[31:28] = triggerinput[0];
assign trigger[27:24] = triggerinput[1];
assign trigger[23:20] = triggerinput[2];
assign trigger[19:16] = triggerinput[3];
assign trigger[15:12] = triggerinput[4];
assign trigger[11:8] = triggerinput[5];
assign trigger[7:4] = triggerinput[6];
assign trigger[3:0] = triggerinput[7];
//---------------------------------------------------------------------------

How can I fix this problem??

thank you

illegal left hand side

1. In this case, write
2.Get a Verilog textbook

illegal left hand side assignment verilog

reg [31:0] trigger;
is only valid if you do it as registered like putting the asignments in a"always" with sensitive to clock.

assign is used for combinational ;
Reg is used for sequential.
As Fvm mentioned you need a good Verilog text book.