dohzer
Member level 1
array type case expression
I'm getting the following error when compiling in ModelSim:
The error points to the first part of the case statement in the following code:
I've seen people having similar problems.
to:
which is effectively the same thing, I don't get an error. I would have thought that since I've declared QUADRANT_WIDTH at compile time, the compiler would be able to handle it.
Is that not the case?
I'm getting the following error when compiling in ModelSim:
Code:
Array type case expression must be of a locally static subtype.The error points to the first part of the case statement in the following code:
Code:
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity amplitude_lookup is
generic
(
TRUNC_PHASE_WIDTH : integer := 16;
QUADRANT_WIDTH : integer := 2;
ADDR_WIDTH : integer := 14;
AMP_DATA_WIDTH : integer := 16
);
port
(
clk : in std_logic;
reset : in std_logic;
trunc_phase : in std_logic_vector(TRUNC_PHASE_WIDTH-1 downto 0);
amp_data : out std_logic_vector(AMP_DATA_WIDTH-1 downto 0)
);
end amplitude_lookup;
architecture sine_lookup of amplitude_lookup is
...
signal quadrant : std_logic_vector(QUADRANT_WIDTH-1 downto 0);
...
begin
...
quadrant <= trunc_phase(TRUNC_PHASE_WIDTH-1 downto TRUNC_PHASE_WIDTH - QUADRANT_WIDTH);
lookup : process(reset, clk, addr, quadrant) is
begin
if(reset = '1') then
amp_data <= (others => '0');
elsif(rising_edge(clk)) then
case quadrant is --<<<< ERROR HERE <<<<
when "00" =>
amp_data <= ...
when "01" =>
amp_data <= ...
when "10" =>
amp_data <= ...
when "11" =>
amp_data <= ...
when others =>
amp_data <= (others => '0');
end case;
end if;
end process;
end sine_lookup;I've seen people having similar problems.
Code:
signal quadrant : std_logic_vector(QUADRANT_WIDTH-1 downto 0);to:
Code:
signal quadrant : std_logic_vector(1 downto 0);which is effectively the same thing, I don't get an error. I would have thought that since I've declared QUADRANT_WIDTH at compile time, the compiler would be able to handle it.
Is that not the case?
