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TCL tutorial or example to write testbench for VHDL code

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cwjcwjcwj

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testbench tcl

I am beginner of using TCL to write testbench for my VHDL code. Anyone have a good tutorial or example that i can start with? thank you very much.
 

Re: fpga testbench tcl

module count (clk, rst, enable, cnt);

input clk, rst, enable;
output [3:0] cnt;

reg [3:0] cnt;

always @(posedge clk or posedge rst) // async active high reset
begin
if(rst)
cnt <= 0;
else if(enable)
cnt <= cnt + 1;
end

endmodule

============================================================

do you know how to use this wan to do a testbench?
 

hi aiko89.. if you want to know how to write a testbench for any given code then check out
WWW.TESTBENCH.IN website.. Here they talk about all verification concepts in detail and sample programs to help you out..
 

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