frozenduck
Newbie level 4
active rc filter
Is it possible to design the filter with cutoff frequency = 100 MHz and the SFDR > 70 DB with 70 MHz Input? The process is 0.35um CMOS.
Is it possible to implement it in active RC?
In active RC, the opamp should have enough loop-gain at 100MHz to ensure the linearuity, right? If I use two stage opamp with 20dB/dec decrease, the GBW will be extreme high. If I use multi-stage opamp, the stability will be an issue. Is there any way to solve the problem?
Or I need to use openloop Gm-C filter? Which one is better for the specs?
Thanks.
Is it possible to design the filter with cutoff frequency = 100 MHz and the SFDR > 70 DB with 70 MHz Input? The process is 0.35um CMOS.
Is it possible to implement it in active RC?
In active RC, the opamp should have enough loop-gain at 100MHz to ensure the linearuity, right? If I use two stage opamp with 20dB/dec decrease, the GBW will be extreme high. If I use multi-stage opamp, the stability will be an issue. Is there any way to solve the problem?
Or I need to use openloop Gm-C filter? Which one is better for the specs?
Thanks.
