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it depends upon the width of clock net where there would be IR Drop if the Width of clock net plays a important role. Its important in calculatiing optimal IR Drop or Voltage drop across the VDD. Fanout is nothing but the drive strength so more the fanout more the voltage drop.
hi kapil,
can you elaborate your answer in relating the clock singnals and the VDD nets drop,
basically my assumption is IR Drop will be measured in Power grid but not in signal nets.
Added after 12 minutes:
hi,
My thoughts go in this way,
If the fan out increases, then the dynamic power increases because of very long slew,shor ckt current increase , which causes to draw more current ,, thinking this may increase IR drop in powergrid
wht i mean to say if width of the clock net is more ..resistance is also more... so Voltage drop is also more. V = IR. I think so.. correct me if i am wrong... but as u said IR Drop is due to power grid so we perform Power Network Analysis and so on...
Other ways of avoiding voltage drop is doing optmization by giving some spacing between std cells and other changes or like reducing congestion by area recovery and finally if nothing works with optmization techniques and recovery techniques then we go about changing the floorplan.
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