Test Bench reading from an extern File on VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_textio.all;

library STD;
use STD.textio.all;

entity tb_suma_2 is
end tb_suma_2;

architecture test_bench of tb_suma_2 is

component suma_2
port(
a,b : in std_logic_vector(1 downto 0);
c : out std_logic_vector(1 downto 0)
);
end component;

signal a, b, c : std_logic_vector(1 downto 0);

begin
cut:suma_2
port map(
a => a,
b => b,
c => c
);

lecturarocess

variable read_len : natural;
variable a_tmp, b_tmp, c_tmp : std_logic_vector(1 downto 0);

type text is file of std_logic_vector;
file vector_file : text open read_mode is "suma.txt";

begin

while not endfile(vector_file) loop

read(vector_file, a_tmp, read_len);
a <= a_tmp;

read(vector_file, b_tmp, read_len);
b <= b_tmp;

end loop;

wait;

end process;

end test_bench;

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