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  1. #1
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    Help me design a 1001/1111 sequence detector

    Hi, I need to design a 1001/1111 sequence detector which produces a 1 output if the current input and the previous three inputs correspond to either the sequence 1001 or 1111. The output 1 is to occur at the time of the forth input of the recognized sequence.

    •   Alt19th July 2009, 16:55

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    verilog codes for sequence detecter

    Use the state machine approach. When the first bit (MSB here) occurs, move to the next state. If the second bit matches, move to the third state and so on till the required sequence is achieved. If, the sequence breaks in any intermediate state go back to initial state. If the sequence matches, in the last state (match state) assert the output. Output is de-asserted otherwise.



    •   Alt19th July 2009, 18:13

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  3. #3
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    verilog coding for sequence detection

    hi radjanohoun,

    Wht exactly are u expecting?? the solution or the approach?
    As far as the approach is concerned as suggested by thiagu.. use State Machines...

    haneet



    •   Alt20th July 2009, 12:55

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  4. #4
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    verilog code for sequence detector

    Hi Haneet,
    Do you need the solution...?
    If so what do you want...? Just the state diagram, the digital circuit or the verilog code for it...?
    If you want to learn to design it by yourself then you have to learn state machines from a good Digital Electronics Book.



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    state diagrams for sequence detector

    Hey Satish..
    itz not me whoz asking Qeries abt state machines... i suggesting abt state machines....

    haneet



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    vhdl code for sequence detector

    Ho Sorry...
    It should probably addressed as radjanohoun.



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