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Need help with buffer design which input varies from 0 - Vdd

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Sadegh.j

Sadegh.j

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Buffer design

Hi

I am trying to design a buffer whose input varies from 0 to Vdd, (almost from zero to almost Vdd) and has a minimum level shift. Any suggestions? The frequency is about 5 Ghz in 0.13um CMOS technology.

Thanks
 

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