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Impedance matching issue- how to match input to a 50&#93

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cmos_vlsi

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Impedance matching issue

I am having the following problem on my class-e amplifier design.
My S-Parameter analysis shows S11=1.004<-158.5 and S22<766.5u<137.4.
If I am correct that's Zin= -0.1034-9.49276i and Zout=49.94358+0.05182i proving that my output is matched to my 50Ω load.
The problem is that I can't figure out how to match my input to a 50Ω source. Using a simple L-match network, QL, RL are negative, Q, LT,CT imaginary and the L-match is not viable.
The method I am using is this one
http://www.circuitsage.com/matching/lowL.pdf
Any help please?
 

Re: Impedance matching issue

S11 > 1 indicates you have an unstable design. Check stability (K, mu).
 

Impedance matching issue

Could you be a little more specific please?

edit: Did some research. I understand know, but how can I improve it's stability?
The weird is that it provides the same s-parameters with a sinusoidical input and a square-pulse input.
 

Re: Impedance matching issue

Dear cmos_vlsi,
Sure your amplifier is not stable. This is indicated by larger-than-one S11 or S22 or negative input or output impedance. In terms of stability analysis, you will find the k-factor smaller than one and\or the stability measure factor is negative in your band.
To stabilize your amplifier, you can apply one of the most convenient methods such as lossy matching (add small series resistance in your matching networks) and negative feedback.
 

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