Verilog -assigning 6 registers value over a serial interface

module Input(
	input Clk,
	input RxD,
	output [31:0]FreqW,
	output [31:0]PW,
	output [31:0]PW2,
	output [31:0]Delay,
	output [31:0]Delay2
	);
	

//////////////////////////////////////////////////////////////////////////////////
//Parameter Declaration.                                                        //
//////////////////////////////////////////////////////////////////////////////////
parameter Increment1K=42949;
parameter Increment1M=42949672;
parameter IDLE=6'b000001;
parameter ADR =6'b000010;
parameter D0  =6'b000100;
parameter D1  =6'b001000;
parameter D2  =6'b010000;
parameter D3  =6'b100000;

//////////////////////////////////////////////////////////////////////////////////
//Reg and Wire Declaration.																	  //
//////////////////////////////////////////////////////////////////////////////////
reg [31:0]FrequencyWord=Increment1M*2;
reg [31:0]Pulse_Width=25;
reg [31:0]Pulse_Width2;
reg [31:0]Delay_Hold=32'h00000005;
reg [31:0]Delay_Hold2;
reg [31:0]Data;
//Byte Counter.
reg [5:0]ByteCounter;
//Data Edge Detector
reg [1:0]DataRdy;
wire DataReady;
//Decoded Address
reg [7:0]Addr;
//UART Wires.
wire RxD_data_ready;
wire [7:0]RxD_data;
wire Baud_Clk;
//////////////////////////////////////////////////////////////////////////////////
//USART Receiver and Decoder.																	  //
//////////////////////////////////////////////////////////////////////////////////

// Instantiate the module
u_rec Receiver (
    .sys_rst_l(1), 
    .sys_clk(Baud_Clk), 
    .uart_dataH(RxD), 
    .rec_dataH(RxD_data), 
    .rec_readyH(RxD_data_ready)
    );

// Instantiate the module
baud Baud_Generator (
    .sys_clk(Clk), 
    .sys_rst_l(1), 
    .baud_clk(Baud_Clk)
    );


//////////////////////////////////////////////////////////////////////////////////
//Data Decoder or Parser																		  //
//////////////////////////////////////////////////////////////////////////////////

//Shift Register to store if Data Ready State.
always@(posedge Clk)
 DataRdy <= {DataRdy[0],RxD_data_ready};
 
//Data Availability Bit.
assign DataReady = (DataRdy == 2'b01) ? 1'b1 : 1'b0;

always@(posedge Clk)
 begin
 if(DataReady) 
  begin
   case(ByteCounter)
    IDLE: 	ByteCounter = ADR;
    ADR : 	ByteCounter = D0;
    D0  : 	ByteCounter = D1;
    D1  : 	ByteCounter = D2;
    D2  : 	ByteCounter = D3;
    D3  : 	ByteCounter = IDLE;
	 default:ByteCounter = IDLE;
   endcase  
  end
 end

always@(posedge Clk)
begin
 if(ByteCounter == ADR)
    Addr   = RxD_data;
 else if(ByteCounter ==  D0)
    Data   = {Data[31:8],RxD_data};
 else if(ByteCounter ==  D1)
    Data   = {Data[31:16],RxD_data,Data[7:0]};
 else if(ByteCounter ==  D2)
    Data   = {Data[31:24],RxD_data,Data[15:0]};
 else if(ByteCounter ==  D3)
    Data   = {RxD_data,Data[23:0]};
end
 
always@(posedge Clk)
begin
  case(Addr)
   8'h41:FrequencyWord = Data;
   8'h42:Pulse_Width   = Data; 
   8'h43:Pulse_Width2  = Data;
   8'h44:Delay_Hold    = Data;
   8'h45:Delay_Hold2   = Data;
   default:FrequencyWord = FrequencyWord;
  endcase
end

assign FreqW = FrequencyWord;
assign PW    = Pulse_Width;
assign PW2   = Pulse_Width2;
assign Delay = Delay_Hold;
assign Delay2= Delay_Hold2;

endmodule