Certificate course on Functional Verification.....

course on systemverilog

Certificate course on Functional Verification
........basics to ASIC verification using SystemVerilog

CVC is announcing a new session of its popular 5-day certificate course on Functional Verification covering SystemVerilog in depth. Broadly it covers the following topics:
 SystemVerilog basics (SVB)
 Verification Using SystemVerilog (VSV)
 Verification Methodology

Duration
Here is a detailed breakdown of the course with duration. Note that we have several “mini projects” tightly embedded in the course that helps in mastering topics learned so far in the course. This is on top of the regular labs that are part of the training.


Topic Duration
SystemVerilog Basics = 0.5 day
Verification using SystemVerilog = 1.5 days
Project I = 0.5 day
Verification Methodology = 1.5 days
Project II = 1.0 day


Schedule:
Tentative: End of June-09 at Bangalore

To attend this class, confirm your registration by sending an email to
training @ cvcblr.com
Ph: +91-9916176014, +91-80-42134156


Please include the following details in your email:
Name:
Company Name:
Contact Email ID:
Contact Number:


Regards
Jagadeesh
www.cvcblr.com