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Bandgap reference design in IBM45nm SOI

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newmedia

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Hello all,
I’m a newbie on analog circuit design, so this might be a stupid question. Please bear with me.

I’m trying to design a bandgap reference circuit for IBM45nm SOI. The specification said ideal supply voltage is 0.9/1.0. However, I want to have a usual 1.25v bandgap reference voltage based on this paper.

AE Buck et. al., "A CMOS bandgap reference without resistors", IEEE Journal of Solid-State Circuits, 2002 [url]http://vergina.eng.auth.gr/electronicslab/el/vlsi/bandgap-jan_2002.pdf

Here is my question. Do you guys think I can apply 3 volt to a supply pad? Technically speaking, applying 3V to the supply pin will not cause problem as far as I know. The reason is that if each transistor in series from VDD to GND experiences a less than 1V, the circuit will not breakdown. Am I right?

I want to know what is the industry practice for low voltage supply chips( below 1V VDD). Do the industry guys use low output voltage bandgap references such as this paper?

H Banba et. al., "A CMOS bandgap reference circuit with sub-1-V operation", IEEE Journal of Solid-State Circuits, 1999 [I]**broken link removed**[/I] Th...tage boosting technique? Thank you, newmedia
 

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