Resistor design -less filter and bias ckt of cp pll question

pll design question

hi :
I want design a charge pump pll. But the process (SOI CMOS) does't provide
resistor device. So , any one can give suggestion on the design of resistor-less filter and bias ckt of cp pll ?

Re: pll design question

Strange, you should have unsilicided poly resistors...

In case you really don't have, you can design the R of the filter with a MOS operating in the linear region. If it is a single-ended flter you can use the source connected to ground and use an other MOS to generate the gate voltage (G and D connected together with a ref current Id flowing inside). Take finger of the same size and make a serial//parallel combinations if you need high R values.
The reference MOS uses transistors in parallel and is operating in strong invertion.
The transistor used as resistor is made of a serial combination (in case you need high resistances) and is working in linear mode.
Write the equations, but if I remember well the equivalent R does not depend of Vt with this biasing but only of sqrt of Id (of the ref tr) and sqrt of beta.

For the current reference, don't use this kind of approach as the eq R is dependant of the current. But here you need only a small R so anything could be used... diffusion, salicided or unsilicided poly, metal etc etc...