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  1. #1
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    vhdl case statement

    when using the case statement for , it displays when others condition is not synthesized.

    is there any alternative for this .

    <code>
    f (STROB1= "01")then


    ADC_DATAMOS_TEMP <= ADC_DATAMOS;

    else
    ADC_DATAMOS_TEMP<= "ZZZZZZZZ";
    end if ;



    process (CLK_MOS,RST_MOS,ADC_DATAMOS,STROB1,RW_MOS)

    begin

    if (RST_MOS='0')then
    ADC_DATAMOS_TEMP <="00000000";


    elsif (RST_DAQ='1') then

    case ADDR_MOS is
    when "00001" => MOS_REG(0) <= ADC_DATAMOS;
    when "00001" => MOS_REG(1) <= ADC_DATAMOS;
    when "00001" => MOS_REG(2) <= ADC_DATAMOS;
    when "00001" => MOS_REG(3) <= ADC_DATAMOS;
    when "00001" => MOS_REG(4) <= ADC_DATAMOS;
    when "00001" => MOS_REG(5) <= ADC_DATAMOS;
    when "00001" => MOS_REG(6) <= ADC_DATAMOS;
    when "00001" => MOS_REG(7) <= ADC_DATAMOS;
    when others =>MOS_REG(8) <= ADC_DATAMOS; -- dummy register ..
    -- DUNNO WHAT TO DO IN - --THIS others PLEASE HELP

    end case ;
    end if;
    end process;

    </code>



    in the above case , i have a set of registers to which a data coming on the line is to be written basing on the address that we recieve .
    What shuld be written when others case ./???

    please help /

    •   Alt9th June 2009, 11:37

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  2. #2
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    vhdl when statement

    Thanks a ton for the quick reply ,
    i was able to remove the synthesis error introducing a null statement in the others case.


    but ,
    the problem is with the warnings :

    Latch generated from process for signal DAQ_REG_6(7 downto 0), probably caused by a missing assignment in an if or case stmt.

    My question to you , is this others stament synthesizable ..?

    If it is null how is it synthesized.

    as i m to target the same to fpga also .



    •   Alt9th June 2009, 12:37

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  3. #3
    FvM
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    case statement vhdl

    O.K. I didn't realize, that the case statement isn't placed within a clock sensitive condition.

    In the case statement, you assign one bit of MOS_REG and leave the others unchanged. This creates a latch anyway, the problem isn't related to the existence of an others statement. It's legal code, but most likely, it doesn't work as expected. For reliable operation, a clock sensitive condition should control the assignment, then a register rather than a latch can be synthesized.



    •   Alt9th June 2009, 13:10

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    vhdl case when

    For reliable operation, a clock sensitive condition should control the assignment, then a register rather than a latch can be synthesized.
    But for some data Read write operations , can we have the operation clock dependent ?

    (as is the case in my above code, i am just performing read write operations on data.)



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    case vhdl

    You could also use:

    When others =>
    MOS_REG<=MOS_REG;

    This will help the synthesizer, but you're still going to get latches. And their outputs are probably going to bounce around.

    I totally agree with FvM: Use a clock.



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    FvM
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    when statement in vhdl

    Remember that VHDL is a hardware description language, not a procedural programming language.
    Check which hardware is generated from your code and if it can give stable data output. In the present
    case, it can't.



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    case in vhdl

    Attention plese : FVM /others

    if i put these statements in a clock sensitive condition , can i ensure that it can generate hardware whch is stable.?

    I m currently using synplify , so i am not able to see what hardware it synthesizes.
    can u please tell me is there anyother tool through which i can also see the synthesized hardware .
    (installed PRecison RTL , awiating License .)



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    when statement vhdl

    If you use a clocked process, and the output of the process is the input to another clocked process, it will be stable (or the tools will tell you if there's a timing error).



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