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  1. #1
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    vco gain

    I am wandering how to decide Kvco in the beginning of the design of your pll?

    It seems for me making Kvco from 1GHz/v to 100MHz/v does not make big difference since I always can find a loop filter to stabilize the loop.

    Is there other conditions that can bound the Kvco?
    Thanks.

    •   Alt3rd June 2009, 19:04

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    vco kvco

    What is your required step size ?
    A VCO at 1GHz per Volt sounds strange, unless you are operating at 60GHz.

    Shouldn't you design or find a VCO that meets your requirements (2nd Har,
    Phase Noise, Stability, Temp Stability...) Then see what it's Kvco is and move
    forward with the design ?

    But I'm no expert, good luck



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    pll vco gain

    I think your VCO circuit will decide the Kvco, and the loop filter size will also decide your Kvco.

    1. Even if you can use any lopp filter size in your simulation, the filter size will be limited by your layout requirements.

    2. Even if you can use any Kvco value, but it does not mean you can make the VCO act like it. So... I'm thinking you have to design a simple VCO, and you have to figure out the a rough estimate of Kvco.

    These are what I am thinking... It might be wrong. :)


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    kvco vco

    Practically speaking, you want the lowest KVCO you can get and still tune over the desired frequency band.

    For instance, it you have a 3 volt power supply, and you need to tune from 2 to 2.3 GHz, you need more than 100 MHz per volt for the vtune range available to cover the entire band.

    If you made the KVCO much bigger than that, lets say 1000 MHz per volt, you would not gain anything by it, and the VCO would be much more susceptable to picking up stray noise.


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    •   Alt4th June 2009, 03:22

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  5. #5
    LvW
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    vco tuning range decide

    Quote Originally Posted by eejli
    I am wandering how to decide Kvco in the beginning of the design of your pll?
    Kvco is only on of some other factors forming the dc loop gain (which is the most important parameter as it influences stability and determines all relevant parametrs).
    Therefore, I think choose an appropriate Kvco as available and correct it - if necessary - by tuning other gain parameters of the loop.


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    pll loop filter design loop gain vco

    Quote Originally Posted by LvW

    Kvco is only on of some other factors forming the dc loop gain (which is the most important parameter as it influences stability and determines all relevant parametrs).
    Therefore, I think choose an appropriate Kvco as available and correct it - if necessary - by tuning other gain parameters of the loop.
    dc loop gain is inf and KVCO can vary by more than 100% for ring VCOs over PVT and output frequency. It is a poorly controlled parameter and the design has to work with that. KVCO has to be made as low as possible without affecting the tuning range requirement to reduce output spurs due to the loop and the supply.


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    vco gain factor for a frequency

    KVCO ideally should be low because the power supply sensitivity of the VCO is lower. Hence your PLL detereministic jitter is lower as well. But on the other side, a high KVCO will also give you a better loop bandwidth which eliminates any lower frequency noise on the VCO. However, with respect to PVT variation being in the high KVCO range is not safe because you cannot really get good numbers with respect to the typical conditions. Faster, low temp corners will give exceeding high gains and slower, high temp corners could give horrible gains. This will effect the stability of the PLL over PVT.

    But ideally have a low VCO gain because any small changes in the VCO control voltage also will not change the frequency output of the VCO.


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    kvco simulation frequency

    thank you guys.

    Yes I agree that Kvco should be small for spur performance.

    If Kvco is defined, then the charge pump current will be defined by the loop bandwidth assuming the divider ration is fixed and the loop cap is 100 pF for layout size reason. Am I right?

    Thanks.



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    how to determine the vco gain in desigining a pll




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