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Divide by 1.5 Counter VHDL Code is here

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Black Jack

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divide by 1.5 counter

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity divide1_5 is

port
(
clk : in std_logic ;
reset : in std_logic ;
div : out std_logic
);

end divide1_5;

architecture struct of divide1_5 is
signal d, q : std_logic_vector (1 downto 0);
-- signal q : std_logic_vector (1 downto 0);
signal fb : std_logic;

begin
process (clk, reset)
begin
if (reset = '0') then
q(0) <= '0';
elsif (clk'event and clk = '1') then
q(0) <= d(0);
end if;
end process;

process (clk, reset)
begin
if (reset = '0') then
q(1) <= '0';
elsif (clk'event and clk = '0') then
q(1) <= d(1);
end if;
end process;

fb <= NOT(q(0) OR q(1));
d(0)<= fb;
d(1)<= fb;
div <= fb;

end;
 

xilinx vhdl code for counter

Other source:

library ieee;
use ieee.std_logic_1164.all;

entity divide1_5 is
port (
gsr : in std_logic;
clk : in std_logic;
divided_clk : out std_logic
);
end entity divide1_5;

architecture rtl of divide1_5 is

signal Q : std_logic_vector(1 downto 0);
signal Q_f : std_logic;

begin

-- divide by 3 counter
divide_by_3 : process (gsr, clk)
begin
if gsr = '1' then
Q <= (others => '0');
elsif rising_edge(clk) then
Q(0) <= not Q(1) or not Q(0);
Q(1) <= Q(0);
end if;
end process divide_by_3;

-- Delay Q1 by half a clock
falling_ff : process (gsr, clk)
begin
if gsr = '1' then
Q_f <= '0';
elsif falling_edge(clk) then
Q_f <= Q(1);
end if;
end process falling_ff;

-- combine the rising and falling edge triggered signals
-- to give an output that has a 1/3 duty cycle, and
-- a frequency of the input clock / 1.5
divided_clk <= Q_f and Q(0);

end architecture rtl;
 

divide by 1.5 counters

Hi all,
You can find a great pdf document from xilinx about dividing a clock by an unusual ratio (1.5 and 2.5 essentially)
good reading

/Post link instead of file.
**broken link removed**
**broken link removed**
(klug)/
 

counter vhdl code

jacklalo020 said:
Hi all,
You can find a great pdf document from xilinx about dividing a clock by an unusual ratio (1.5 and 2.5 essentially)
good reading

Direct link:
h**p://www.xilinx.com/xcell/xl33/xl33_30.pdf
 

vhdl divide package

Hi,

This link gives a schematic version of a 1.5 divider :

h**p://www.discovercircuits.com/PDF-FILES/divider1.pdf

* = t
 

design of divide by 1.5 counter

The ratio is 1.47.
 

vhdl divide 1.5

hi

i tried to understand the PDF but couldnot follow it properly.i am not able to understand the effect of combinational loopback...

how to analyze the combination loopback circuit. any help would be greatful since i am not able to give much time towards it.
 

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