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Clock generation with JK flip flop

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jk flip flop clock

I am utilizing a 26 MHz TCXO along with a JK flip flop to generate a 13MHz clock that is needed for another IC. My question is on what pin of the JK Flip Flop do I connect the 26 MHz TCXO? Clock, J or K?
 

54ls107 toggle frequency

If your using this IC (SN74/54LS107) then connect your oscillator to the clock pin and tie J,K and clear (CLR) high. the output will toggle on the falling edge (divide by 2)
 

sn74 j k

trekkytekky said:
If your using this IC (SN74/54LS107) then connect your oscillator to the clock pin and tie J,K and clear (CLR) high. the output will toggle on the falling edge (divide by 2)
Click to expand...

will connecting J,K and clear (CLR) to VCC be good enough?
 

how clock work in jk flip flop

Connecting to Vcc would be fine, it will pull the inputs high. Just be aware that the 107 has a minimum clock low duration of 47nS and a max frequency 30MHz from the datasheet you posted. So your tcxo may be to fast for it depending on the duty cycle of its output. Only way to find out for sure is to try it and see. If it does work the output of the Flip Flop will be a 50% duty cycle, irrespective of the input duty cycle.
 

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