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Memory Modelling in RTL using Verilog - help needed

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rockskuller

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Memory Modelling in RTL

I need to synthesize Instruction and Data memory modules. How can it be modelled in RTL using Verilog.

In fact for behavioral memory modelling I use reg [wordsize:0] array_name [0:arraysize]
 

Re: Memory Modelling in RTL

Thanks a lot!
 

Memory Modelling in RTL

Hi you can use some tools to generate the memory modeling. including all the format
 

Re: Memory Modelling in RTL

@rsqf

Can you mention those tools name?
 

Re: Memory Modelling in RTL

rockskuller said:
@rsqf

Can you mention those tools name?
Click to expand...

such as Artisan memory compiler, xilinx mempry compiler .
 

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