switched capacitor circuit in cadence

cadence switched capacitor

Hi
I am trying to design a switched capacitor sampling system in virtuoso schematic editor. But I don't know how to:
1- Generate non-overlapping clocks.
2- How to model the switches? should I use like nfet or there are special switches?

Thank you,
M

switched capacitor cadence

mahyar said:

Hi
I am trying to design a switched capacitor sampling system in virtuoso schematic editor. But I don't know how to:
1- Generate non-overlapping clocks.
2- How to model the switches? should I use like nfet or there are special switches?

Thank you,
M

Click to expand...

1:non-overlapping clocks can be generated by VPWL, also can be generated by sircuits
2: u can use ideal switch or NMOS or pMOS or Xgates depending on practical case u want

Also you can apply the VPWL to a series of buffers (inverter chain) to get realistic rise and fall behavior applied to the switched capacitor circuit

Re: switched capacitor cadence

Hi
1. For generating non-overlapping clock use VPWL as suggested. I will suggest to use 2 VPwl having duty cycle less than 50%. For the first clock do not use any delay and for the 2nd clock use delay to generate non-overlapping pulses.

2. For starting the simulation ( for learning step by step) I would suggest initially use ideal switch then go for NMOS/PMOS.

fanatic said:

mahyar said:

Hi
I am trying to design a switched capacitor sampling system in virtuoso schematic editor. But I don't know how to:
1- Generate non-overlapping clocks.
2- How to model the switches? should I use like nfet or there are special switches?

Thank you,
M

Click to expand...

1:non-overlapping clocks can be generated by VPWL, also can be generated by sircuits
2: u can use ideal switch or NMOS or pMOS or Xgates depending on practical case u want

Click to expand...