cvc.training
Newbie level 4
Quick facts:
When: June 1st 2009, 4PM to 6PM
Where: Board Room, Mentor Graphics, Hyderabad
Agenda: 1 hour: SystemVerilog language tutorial. 45 min: Case study, 15 min: Q&A
Who: Srinivasan Venkataramanan, Chief Technology Officer, CVC Pvt. Ltd.
Cost: No cost, but limited space, first-come-first-serve
IEEE 1800, SystemVerilog is a major extension to Verilog-2001, adding significant new features to Verilog for verification, design and synthesis. Enhancements range from simple improvements to existing constructs, addition of new language constructs to the inclusion of
complete Object-Oriented features. With extensive support from all major EDA vendors, SystemVerilog is the most preferred Design-Verification language in the industry today.
We at CVC (www.cvcblr.com) have been on the top of leading edge verification technologies for the past half-a-decade. As part of our Verification on Wheels (VoW) series, we are pleased to announce a 2-hour seminar on SystemVerilog in action.
Agenda:
Introduction to SystemVerilog
Quick-fire SystemVerilog language tutorial
Sample applications of SystemVerilog to domains like: Networking, processor, image processing
Case study on a complex cross point fabric design
Lucky draw – one winner gets a book on SystemVerilog
To attend this seminar, confirm your registration by sending an email to events@cvcblr.com with subject as VoW_HYD Seminar. Please include the following details in your email.
Name:
Company Name:
Official Email ID:
Role:
Contact Number:
Venue:
Mentor Graphics India Pvt Ltd.
Board Room, 6-3-552, Sri Ram Towers
Somajiguda, Hyderabad- 500082
Ph: 040 66374000
Brief Bio:
Srinivasan Venkataramanan, Chief Technology Officer, CVC Pvt. Ltd.
https://www.linkedin.com/in/svenka3
Over 13 years of experience in VLSI Design & Verification
Designed and Verified ASICs from block level to SoC. Also involved in behavioural modelling for ADC/DAC etc.
Architected, implemented several pre-Si verification environments for various domains: Networking, communication & image processing
Co-authored leading books in the Verification domain.
Worked at Philips, RealChip, Intel, Synopsys in various capacities.
Involved in VMM base class development
Presented papers, tutorials in various conferences, publications and avenues.
Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV and OOP for Verification
Holds M.Tech in VLSI Design from prestigious IIT, Delhi.
Regards
Jagadeesh
When: June 1st 2009, 4PM to 6PM
Where: Board Room, Mentor Graphics, Hyderabad
Agenda: 1 hour: SystemVerilog language tutorial. 45 min: Case study, 15 min: Q&A
Who: Srinivasan Venkataramanan, Chief Technology Officer, CVC Pvt. Ltd.
Cost: No cost, but limited space, first-come-first-serve
IEEE 1800, SystemVerilog is a major extension to Verilog-2001, adding significant new features to Verilog for verification, design and synthesis. Enhancements range from simple improvements to existing constructs, addition of new language constructs to the inclusion of
complete Object-Oriented features. With extensive support from all major EDA vendors, SystemVerilog is the most preferred Design-Verification language in the industry today.
We at CVC (www.cvcblr.com) have been on the top of leading edge verification technologies for the past half-a-decade. As part of our Verification on Wheels (VoW) series, we are pleased to announce a 2-hour seminar on SystemVerilog in action.
Agenda:
Introduction to SystemVerilog
Quick-fire SystemVerilog language tutorial
Sample applications of SystemVerilog to domains like: Networking, processor, image processing
Case study on a complex cross point fabric design
Lucky draw – one winner gets a book on SystemVerilog
To attend this seminar, confirm your registration by sending an email to events@cvcblr.com with subject as VoW_HYD Seminar. Please include the following details in your email.
Name:
Company Name:
Official Email ID:
Role:
Contact Number:
Venue:
Mentor Graphics India Pvt Ltd.
Board Room, 6-3-552, Sri Ram Towers
Somajiguda, Hyderabad- 500082
Ph: 040 66374000
Brief Bio:
Srinivasan Venkataramanan, Chief Technology Officer, CVC Pvt. Ltd.
https://www.linkedin.com/in/svenka3
Over 13 years of experience in VLSI Design & Verification
Designed and Verified ASICs from block level to SoC. Also involved in behavioural modelling for ADC/DAC etc.
Architected, implemented several pre-Si verification environments for various domains: Networking, communication & image processing
Co-authored leading books in the Verification domain.
Worked at Philips, RealChip, Intel, Synopsys in various capacities.
Involved in VMM base class development
Presented papers, tutorials in various conferences, publications and avenues.
Conducted workshops and trainings on PSL, SVA, SV, VMM, E, ABV, CDV and OOP for Verification
Holds M.Tech in VLSI Design from prestigious IIT, Delhi.
Regards
Jagadeesh