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Clock task from Verilog to VHDL

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karper1986

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task vhdl

Hello, how can I declare from verilog -->> to VHDL
initial
clk = 1'b0;
always
clk = #10 ~clk;

Thanks.

Added after 10 minutes:

And these
`define RESET_TIME 8

initial
reset = 1'b1;
task reset;
begin
reset <= #1 1'b1;
tk_wait(`RESET_TIME);
reset <= #1 1'b0;

task tk_wait;
input[31] count;
integer i;
begin
for(i=0;i<=count;i=i+1)
@(posedge clk);
end
endtask

Added after 3 minutes:

Anybody, please help me in solution these a little problem, cause I`m new in VHDL.
 

verilog & clock & task

Checkout this.............

Code: 
signal clk : std_logic := '0';
clk <= transport not clk after 10 ns;

constant RESET_TIME : integer := 8;

signal reset : std_logic := '1';

procedure reset_dut () is
begin  -- reset_dut
reset <= transport '1' after 1 ns;
tk_wait(RESET_TIME);
reset <= transport '0' after 1 ns;
end reset_dut;

procedure tk_wait (variable rst_time : in integer;) is
begin  -- tk_wait
    for i in 0 to rst_time loop
      wait until (clk'event and clk='1');
    end loop;  -- i
end tk_wait;
 

    K

    karper1986

    Points: 2
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