+ Post New Thread
Results 1 to 2 of 2
  1. #1
    Newbie level 1
    Points: 640, Level: 5

    Join Date
    May 2009
    Posts
    1
    Helped
    0 / 0
    Points
    640
    Level
    5

    Sequential design in VHDL

    Hi,

    I need to design a circuit using 2 positive edge-triggered t flip flops w/synchronous active high reset and CE. The inputs that I am given are INPUT, CLR and CLK and the outputs are Q0, Q1 and RCO. Here's what I have for the code so far:



    Code:
    entity sequential is
        Port ( INPUT : in  STD_LOGIC;
               CLR : in  STD_LOGIC;
               CLK : in  STD_LOGIC;
               Q0 : buffer  STD_LOGIC;
               Q1 : buffer  STD_LOGIC;
               RCO : out  STD_LOGIC);
    end sequential;
    
    architecture Behavioral of sequential is
    signal CE0: STD_LOGIC;
    signal CE1: STD_LOGIC;
    
    begin
    
    process (CLK)
    begin
       if CLK'event and CLK='1' then  
          if CLR='1' then   
             Q0 <= '0';
          elsif CE0 ='1' then
             Q0 <= not(Q0);
          end if;
       end if;
    end process;
    
    process (CLK)
    begin
       if CLK'event and CLK='1' then  
          if CLR='1' then   
             Q1 <= '0';
          elsif CE1 ='1' then
             Q1 <= not(Q1);
          end if;
       end if;
    end process;
    end Behavioral;
    I need to add code to my design to generate the flip flop excitations (CE0 and CE1) and the output (RCO). This is the part I am getting stuck on. Did I do the right thing and replace <clock enable> in the skeleton code for the t flip flop with CE0 and CE1? Also, should I declare CE0 and CE1 as signals like I did above? I am not sure how to generate CE0 and CE1 excitations but I was thinking something along the lines of CE0 <= CLK and INPUT. Is that correct? If so, would I do CE1 <= CLK and Q0? Where does RCO come in in all of this?

    Thanks!

    •   Alt17th May 2009, 20:03

      advertising

        
       

  2. #2
    Newbie level 1
    Points: 638, Level: 5

    Join Date
    May 2009
    Posts
    1
    Helped
    0 / 0
    Points
    638
    Level
    5

    Re: Sequential design in VHDL

    CE0 and CE1 should be the j/k ff (T FF)input equations, your declaration is correct, you need to assign values for them.. look at project one for the equations.. RCO is your 3 to 8 decoder selected output... as far as i remember its something like q0 and q1 and input or the q0' q1' and input' because you select y0 and y7 from the decoder.. the only thing i am not sure of is the clock enable thing.. thats actually how i got to this page, was googling stuff hoping to find what that clock enable thingy is.. limme know if you figure that clock_enable thing out.. gluck :)



+ Post New Thread
Please login