Hello Everybody,

I need some help, and it's a little bit pressing

I am co-simulating a design with vhdl - systemC

I have a :
1) systemC file which generates stimuli (stimuli.h)
2) a vhdl source cordic_pipline.vhd
3) a top level file cordic.vhd which instanciate the latter ( cordic_pipline.vhd ).
and a top level systemC file : main.cpp file

here is my makefile:

Code:
all :
	mkdir WORK
	vhdlan cordic_pipeline.vhd
	vhdlan cordic.vhd
	vhdlan -sysc cordic.vhd -sc_model cordic -sc_portmap cordic.map -cpp g++
	syscsim -mhdl main.cpp -cpp g++ -cc gcc -debug
	./simv -gui
	#vhdlan -spc cordic.vhd
	#design_vision
clean:  
	rm -f -r csrc
	rm -f -r WORK
the problem is when I truy to debug and see internal signals using DVE, I get an error message saying:



Code:
Error: [DVIT005] 
UCLI command 'ucliGUI::vpdAddHierarchy -scope cord.CORD -depth 2 -file /users/enseig/houfaf/Desktop/CORDIC_FINAL_TERT/PIPELINE/inter.vpd; synopsys::dump -flush VPD0' failed: 
'Error-[UCLI-CMD-SCOPE-NOT-FOUND] Scope not found
  The specified scope "cord.CORD" is not found.  
  Please enter 'show [-instances|-scopes]' to see valid scopes in the design 
  hierarchy of interest.'.
I am sure I need to turn on an option to dump the internal signals or something like that ... but I can't find it

Can somebody help me please

Thanks in advance


// Edit By in ternal node I mean, nodes belonging to the instances of my design, all I can see right no are signals of the top level module.
here a snapshot of the GUI